Google plans to deploy two new variants of its TPU accelerators next year, intended for its cloud and, potentially, for a few customers who might get hardware for their own data centers. These are the TPU 8tx and TPU 8i Max, derived from the Sunfish (TPU 8t) and Zebrafish (TPU 8i) chips that Google unveiled in April.
The TPU 8t is manufactured by Broadcom’s chip division and is expected to already be entering Google’s data centers. The TPU 8i is designed with MediaTek, which experienced delays earlier this year, and it is not certain if it has already been delivered to Google. The modified versions are expected to be installed in 2027. According to the analysis author, a launch in the first quarter of 2027 is conceivable, with a ramp-up over about a year and a half. Such timelines are common: the Ironwood TPUs (v7p), deployed internally in the fourth quarter of 2025, were only offered for rent on Google Cloud about a year later, when excess capacity was sufficient. Their pricing is now published for the US-Central1 (Iowa) and Europe-West2 (London) regions.
The TPU 8t, for Training
The TPU 8t is designed for training workloads. Its 3D torus interconnect links up to 9,600 accelerators in a shared and coherent memory space, for a claimed performance of 121 exaflops at FP4 precision. Mark Lohmeyer, Vice President and General Manager of AI and Compute Infrastructure at Google, indicated on a conference call that these machines are grouped into pods of 9,600 units, then assembled into a cluster of over 1 million TPU 8t devices. This cluster is said to have been used to train Gemini 4 Carbon, developed by the DeepMind division and announced on October 28.
For API access via Google Cloud, both Gemini 4 Carbon and Gemini 4 Argon have an “introductory price” of $2 per million input tokens and $10 per million output tokens. Cached input tokens are billed at a 95% discount compared to the input token price.
The TPU 8tx and TPU 8i Max, for Inference
The TPU 8tx is a variant of the TPU 8t geared towards inference, meaning running models once trained, although it can also be used for training during idle periods. Google replaces the 3D torus with a boardfly interconnect, a variant of the dragonfly topology that the company designed itself. The pods thus shrink from 9,600 to 1,152 accelerators. According to the published analysis, the average latency of this system would be about half that of the 3D torus topology. The Axion server processor, based on Arm architecture, is also replaced by an AMD Epyc processor whose model is not named. This choice is explained by the integrated encryption and root-of-trust accelerators in these processors, which allow data to remain encrypted until processing.
The TPU 8i Max, meanwhile, targets workloads with long contexts. It doubles the number of Zebrafish complexes per socket, but the HBM memory capacity per socket only increases by 33% compared to the original TPU 8i. Each chip in the original TPU 8i had 288 GB of memory, compared to 192 GB per chip for the TPU 8i Max, with an unchanged bandwidth of 8.6 TB/s. This configuration spreads the memory across more chips, which are coupled to form a larger shared memory.
TPU Sync, Memory Management
Google has also developed TPU Sync, a software layer for hierarchical memory management that operates on top of the TPUs. “This means TPUs are often idle a lot of the time,” explained Mark Lohmeyer. “If we were to keep these resources allocated even when they’re not being used, it would create huge inefficiencies, especially as these agentic workloads really start to ramp up.” According to him, TPU Sync moves working memory off-chip when an agent pauses, then restores it when processing resumes. As it is software, Google can apply it to previous generations, and the company has done so for TPUs 5, 6, 7, and 8. The analysis notes that the inference throughput gain provided by TPU Sync has not been quantified.
