Google is expanding its range of AI-dedicated accelerators with the TPU 8tx and TPU 8i Max, unveiled on November 9, 2026. These two configurations complete the eighth generation of Tensor Processing Units (TPU), the chips designed by the group for artificial intelligence computations, and address two distinct challenges: securing the processing of sensitive data and managing workloads requiring significant memory.
This announcement brings the number of eighth-generation TPU systems unveiled by Google in 2026 to four. In April, the group had introduced the TPU 8t, intended for training large models, and the TPU 8i, optimized for inference and low-latency reasoning, meaning for producing responses with reduced delay.
Two TPUs for confidentiality and large-scale processing
The TPU 8tx targets businesses and administrations that wish to run AI models and autonomous agents on sensitive data. Google highlights sectors subject to regulatory requirements, for which the confidentiality of information during its processing is a major issue. On the hardware side, the system reuses the silicon from the TPU 8t and integrates fifth-generation AMD EPYC host processors. It also incorporates hardware security mechanisms designed to protect data and model weights, meaning the parameters that define their operation, during their use in memory, and not only when they are stored or transmitted over the network.
Google pairs the TPU 8tx with its Boardfly network, designed for low-latency communications. According to the provider, this architecture can reduce latency by up to half compared to the TPU 8t, without significant performance degradation. The configuration should allow businesses to perform multiple operations on the same infrastructure, including training, fine-tuning on private data, meaning adapting a model to a specific dataset, model distillation, and reinforcement learning for AI agents.
The TPU 8i Max, on the other hand, addresses applications that require significant memory resources. Google cites agents capable of analyzing large codebases, long video sequences, or contexts exceeding one million tokens, tokens being the units of text that models manipulate. To increase available resources, the manufacturer has grouped two TPU 8i chips into a single package. Compared to the TPU 8i, this configuration doubles the computing capabilities, SRAM memory, and HBM memory bandwidth. Google also indicates that it allows integrating twice as much silicon into the same rack footprint, meaning the space occupied by a server bay.
Google wants to open its TPU ecosystem further
Alongside these hardware announcements, Google continues to open its software environment. The group indicates that TorchTPU, published as open source, allows running PyTorch code and Hugging Face models on its accelerators. Integrations are also offered for the vLLM and SGLang inference engines. A TPU agent suite is also available in preview. It is intended to automate certain integration, diagnostic, and kernel optimization operations, these small programs that execute computations on the chips. Google announces that this suite is compatible with several development tools, including Claude Code, Cursor, and Google Antigravity.
The provider also introduces TPU Sync, a software layer intended to unify the management of HBM memory, host DRAM memory, and shared storage. It should notably facilitate the transfer of KV caches, used by generative models to accelerate text production. Google claims this technology can reduce certain latencies associated with these transfers and the first token generation time by more than 90%.
Finally, Cloud Pathways is now generally available on Google Kubernetes Engine (GKE). The solution allows orchestrating distributed workloads across multiple TPU pods from a single controller.
