Microsoft detailed the specifications of its upcoming Maia 300 AI accelerator, named “Clea”, at the Open Compute Project Summit 2026. Designed for inference, meaning running models once trained, this specialized processor (XPU) is intended to run generative AI and larger agentic workloads faster.
- Microsoft presents Maia 300, an inference chip named Clea, designed to run generative AI and agentic workloads faster.
- The package combines seven chiplets with 288 GB of HBM4 memory and is manufactured by TSMC on a 2-nanometer process.
- Each rack holds 96 accelerators, so 128 racks can operate as a single system with 12,288 accelerators.
- Microsoft claims up to seven times the token throughput of Maia 200 racks and 2.5 times better performance per watt, although these figures are unverified.
Microsoft has been designing its own chips since 2023, with the Maia 100, named “Athena”, unveiled in November 2023. The Maia 200, called “Braga”, was revealed in January 2026 and is entering production on Azure this year. In a separate announcement, Scott Guthrie, Microsoft’s Executive Vice President for Cloud and AI, stated that the “multi-generational Azure Maia program has become a fundamental element of Microsoft’s AI infrastructure strategy”. Maia 200 chips are already handling inference for Copilot and helping Microsoft’s AI team develop new models. GitHub Copilot and Microsoft Foundry are set to migrate to these chips by year-end, with Foundry running OpenAI’s models, Microsoft’s models, and several open-source models.
A chip composed of multiple elements
The Maia 300 is not a single chip in the strict sense, but a package of seven chiplets and eight stacks of HBM4 memory mounted on an interposer. It is manufactured on a 2-nanometer process (N2P) by TSMC, whereas the Maia 200 used a 3-nanometer process. Its chiplet architecture separates the input-output and memory controllers from the compute core. Microsoft states the package includes 288 GB of HBM4.
According to analyst estimates, the package size would be approximately 1,980 mm², compared to 810 mm² for the Maia 200, and the transistor count would be around 280 billion, excluding HBM4 memory. These figures do not come from Microsoft. HBM memory bandwidth is also estimated at 18 TB/s, with a combined SRAM bandwidth, a very fast cache memory, of about 166.2 TB/s. Microsoft also organizes memory in a particular way: each pair of compute tiles is connected to a pair of HBM4 banks, and the memory is not explicitly shared across all tiles.
Denser racks
Maia 300 servers move from a 2U to a 1U form factor, doubling the number of accelerators per rack to 96 XPUs. Microsoft indicates a rack consumes approximately 167 kW. By connecting 128 racks, you get 12,288 accelerators in a single system image, a coherence domain larger than those announced so far by major cloud players, and larger than the 72 or 144 GPUs that Nvidia and AMD connect coherently in their rack-scale systems.
In their technical presentation, Rani Borkar, President of Azure Hardware Systems and Infrastructure, and Saurabh Dighe, Corporate Vice President of System Planning and Architecture, claim that a rack of 96 Maia 300s delivers up to seven times the “token throughput” of a rack of 48 Maia 200s. They also cite a 2.5x improvement in performance per watt, a metric the source presents as the most notable of the announcement. These figures are performance claims by Microsoft and have not been independently verified.
